1. Field of the Invention
The present invention related generally to a synchronization unit for synchronizing two system clocks in an electronic device, such as a switching device.
2. Description of the Related Art
For satisfying increased operational dependability in switching technology, it is demanded that two processor assemblies (one of the two is a master and the other is a slave) work redundantly. This can be achieved by micro-synchronous operation, whereby the slave synchronizes to the master. The master in turn synchronizes to an external reference clock. Given an outage of the external reference clock, the (clock) master must continue to work for example, in a (hold over mode) and the slave must continue to synchronize to the master.
The critical demand for micro-synchronous operation is that the phase difference between the two processor assemblies should lie within an extremely slight time difference (for example, 5 ns).
Synchronization methods wherein phase information are exchanged between the two processor assemblies can be imagined for satisfying the demand. In these methods, however, falsifications of the phase information can occur due to different gate running times and reflections on the connecting lines between the two assemblies. This leads to operating instabilities.
The European patent document EP 0 175 888 A discloses a synchronization means using a phase comparator with each incoming channel to compare the clock phase of the incoming signal and a local oscillator. The phase comparator of the active unit generates a signal to control the oscillator to maintain its output in phase with incoming signal. The oscillator is a voltage controlled quartz oscillator.